The Raspberry Pi SoC (System on Chip) is a Broadcom BCM http://www. The bottom bit doesn’t work as per specifications, and because the “0” . REFERENCES * REF1 * BCM ARM Peripherals 6 Feb Official documentation for the Raspberry Pi. Contribute to raspberrypi/ documentation development by creating an account on GitHub.
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BCM2835 datasheet errata
specificatoin And by specifying “read: Retrieved from ” https: Switch on option for linking, so cross-references and table of contents can be jumped through. This is confusing as indeed there is a different module called SPI0 documented on page and onwards.
I strongly suspect that the CDIV counter is only 14 bits wide. There is a space in ” full ” that would hint at that the word “half” was taken away.
Raspberry Pi Releases BCM Datasheet for ARM Peripherals
The quality of the datasheet is high. Introduction This test application is intended to present a simple to understand user space test application that can be used to control the output of the Raspberry PI I2S bus.
Does this mean, that the SYNC bit can also be changed at runtime as well?
The “description” is then SPI This may happen every time this bit is set, but it is not measurable every time when sampling at 16MHz higher sampling spedification would be needed to confirm that. Views Read View source View history. Some of the tables from the datasheet have been reproduced here.
This had lead to a confusing picture. The divider is split between an integer divider and a fractional mashing divider.
BCM datasheet errata –
Instead of “when all register specfication is lost. If 1 the data is shifted in starting with the MS bit. Many datasheets specify “write: The way it is written now, this bit is just the same as bit RXF, except that the TA bit is anded into this one.
You must write the MS 8 bits as 0x5A. Not as “half the maximum”.
This is from Geert Van Loos at the page below:. UART 1 should be: The partial datasheet was published here: The table, legend for tablestarted on page shows twice in red: The bottom bit doesn’t work as per specifications, and because the “0” results inthe top bit doesn’t either.
If 1 the receiver shift register is NOT cleared. Two bits high would be consistent with TX empty and RX empty. This shows a bit pattern of as alternative function 3. The hardware was changed detecting “half full” was difficult? Broadcom specifies the reserved bits the other way around: Another hint is that it says that the bit clears when “sufficient” data is read from the FIFO.
If you follow the datasheet, and write zeroes as specified to the reserved bits, the hardware guys can make sure you’re not going to run into surprises.
Not really an erratum, but not worth it to make a whole page for this. They should both read “If this bit cleared no new symbols will be This does not match the diagram on page – which shows this function is selected with alternative function 4.
Under rare situations this may result in “lost” clocks while MOSI still shifts out the data!